1. Field of the Invention
The present invention relates to a data access method, and more particularly to a data access method for serial bus.
2. Description of Related Art
A flash memory is a common storage element used on the mainboard, and has been broadly applied in the personal computers and notebooks. The flash memory can store various types of data, and can be controlled by an embedded controller such that other control chips on the mainboard can write data in the flash memory, or read the data stored in the flash memory. Taking the broadly applied computer architecture as an example, the embedded controller and the flash memory are connected through a Serial Peripheral Interface (SPI), and the embedded controller is also connected to a south bridge chip on the mainboard through a Low Pin Count Bus (LPC Bus).
When it is required to write data in the flash memory, the south bridge chip writes the data to the embedded controller with a write cycle in the LPC Bus, and after the embedded controller receives and stores the data transmitted from the south bridge chip, it writes the data in the flash memory with a programming cycle in the SPI.
In the conventional art, a plurality of bytes is written in each programming cycle such that the SPI can write the data in the flash memory effectively and rapidly. Taking writing 256 bytes in a programming cycle as an example, the timing of each pin in the SPI is as shown in FIG. 1. FIG. 1 is a timing diagram of the programming cycle of the SPI according to the conventional art.
Referring to FIG. 1, SCK, SCE#, SI, SO are all pins of the SPI, wherein a clock signal is on the SCK pin, an enable signal is on the SCE#, the data transmitted from the flash memory to the embedded controller is on the SO pin, and the data transmitted from the embedded controller to the flash memory is on the SI pin. It can be seen from FIG. 1 that, an instruction of 8 bits is transmitted on the SI pin first, and the instruction is transmitted by the embedded controller to the flash memory. Next, 24 bits transmitted on the SI pin is an initial address of the written data. Afterwards, the bits transmitted on the SI pin are all the data to be transmitted by the embedded controller to the flash memory.
It can be seen from the programming cycle that, the embedded controller writes the data of a plurality of bytes in each programming cycle. Therefore, a plurality of registers is built in the conventional embedded controller. After several write cycles in the LPC Bus, the data of a plurality of bytes from the south bridge chip is stored in the plurality of registers, such that the embedded controller can write the data of a plurality of bytes in the flash memory in the same programming cycle.
Similarly, when it is required to read the data in the flash memory, the embedded controller receives the data of a plurality of bytes in the flash memory in the same cycle, stores the data in the internal registers, and then output the data of a plurality of bytes in the plurality of registers to the south bridge chip through several read cycles in the LPC Bus.
However, as a plurality of registers must be built in the embedded controller to transmit the data of a plurality of bytes in one cycle. Moreover, when the data transmission volume predetermined in the cycle increases, the number of registers in the embedded controller increases, such that the registers waste a large amount of cost of the embedded controller. Additionally, the plurality of registers in the embedded controller also causes a large area of the integrated circuit.